1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a capacitor for a mixed-mode circuit device.
2. Description of the Related Art
A mixed-mode circuit device typically includes a circuit comprising both digital and analog devices on a logic area of a semiconductor chip. The digital devices include inverters, adders, and the analog devices include amplifiers and analog-to-digital converters. The digital and analog devices further comprise elementary devices such as MOS transistors and capacitors.
Typically, the process for manufacturing the MOS transistor and the capacitor in the mixed-mode circuit device comprises the steps of forming an insulating layer on the substrate to define an active region of the MOS transistors. A field oxide layer is formed on the substrate to isolate the adjacent devices from each other. A patterned first conductive layer used as the bottom electrode of the capacitor is formed on the field oxide layer. Then, a thermal oxidation process is performed to simultaneously form a gate oxide layer on the active region and an oxide layer on the top surface and the sidewall of the patterned first conductive layer. Next, a second conductive layer is formed over the substrate. Thereafter, the second conductive layer is patterned to form a gate electrode on the gate oxide layer and an upper electrode of the capacitor on the oxide layer above the bottom electrode.
However, after the second conductive layer is patterned to finish the process for fabricating the capacitor, conductive residuals with a size of about 0.4-0.5 micrometers remain on the substrate around the bottom comer of the patterned first conductive layer, which is the bottom electrode. The conductive residuals lead to the bridging effect between two gates respectively belonging to two adjacent MOS transistors. Because of the bridging effect, the faulty operations of the devices easily occur, the functions of the devices fail and the yield is low.
Usually, in order to overcome the bridging problem caused by the conductive residuals, a relatively large allowance space between the MOS transistor and the capacitor in the mixed-mode circuit device according to the design rule is used to avoid the bridging effect. Nevertheless, the relatively large allowance space disrupts the enhancement of the integration of the devices and lead to the consumption of the wafer spaces.
Moreover, in a conventional mixed-mode circuit device, the capacitors are centrally formed in the same region on the wafer, so that the wires used to respectively electrically couple the capacitors and the MOS transistors are very long. This leads to the increase of the resistor capacitor time delay (RC time delay). In order to overcome the problem caused by the long wires, the capacitors are formed apart in the different region on the wafer to decrease the distance between the capacitors and the MOS transistors. Therefore, the length of the wires and the RC time delay can be reduced. Nevertheless, since the capacitors are formed apart in the different region on the wafer, the bridging effect between two adjacent gates due to the conductive residuals becomes more serious and the yield becomes lower. Additionally, the integration is greatly disrupted by the allowance spaces according to the design rule.